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LPC47N237
3.3v I/O Controller for Port Replicators and Docking Stations
Data Brief
Product Features
3.3 Volt Operation (5V Tolerant) 32 SMBus-Hosted General Purpose Input/Output Pins
- SMBus Slave Controller Enables Read/Write Access to GPIO Ports - SMBus Runs on and GPIO Pins are Driven by Suspend Supply (VTR) - SMBus Interrupt Pin - SMBus Isolation Circuitry
Serial Port
- Full Function Serial Port - High Speed 16C550A Compatible UART with 16-Byte Send/Receive FIFOs - Programmable Baud Rate Generator supports 230k and 460k Baud - Modem Control Circuitry - 480 Address and 15 IRQ Options - Ring Indicator Wakeup Event
PC99a/PC2001 Compliant ACPI 1.0/2.0 Compliant Power Management Interface LPC Interface
- Multiplexed Command, Address and Data Bus - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - nIO_PME pin for UART Ring Indicate - PCI Clock Run Support
Multi-ModeTM Parallel Port with ChiProtectTM
- Standard Mode IBM PC/XT(R), PC/AT(R), and PS/2TM Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry for Protection - 480 Address, Up to 15 IRQ and Three DMA Options
XNOR-Chain 100 pin TQFP lead-free RoHS compliant package
4 LPC-Hosted General Purpose Input/Output Pins
SMSC DB - LPC47N237
Revision 0.3 (03-30-07)
PRODUCT PREVIEW
ORDERING INFORMATION
Order Number: LPC47N237-MT for 100 pin TQFP lead-free RoHS compliant package
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.3 (03-30-07)
Page 2
SMSC DB - LPC47N237
PRODUCT PREVIEW
General Description
The LPC47N237 is a 3.3V (5V Tolerant) PC99a/PC2001 compliant Docking I/O controller. The device, which implements the LPC interface, includes I/O functionality. LPC47N237's LPC interface supports LPC I/O and DMA cycles. There is also a SMBus hosted GPIO Block. The LPC47N237 provides 4 LPC general purpose pins which offer flexibility to the system designer. The legacy I/O included in the LPC47N237 are: a 16C550A compatible UART; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47N237 incorporates sophisticated power control circuitry (PCC) which includes support for PME. The PCC supports multiple low power-down modes. The LPC47N237 is ACPI 1.0b/2.0 compatible. The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47N237 may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels. The SMBus hosted GPIO Block includes 32 GPIOs that are powered by standby supply. The GPIOs can be used to assert an interrupt on a change in state of a GPIO. These events are indicated on the nSMBINT pin. IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation. SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation.
SMSC DB - LPC47N237
Page 3
Revision 0.3 (03-30-07)
PRODUCT PREVIEW
Block Diagram
VTR
16C550A UART
PCI_CLK nPCI_RESET LAD[3:0] nLFRAME nLDRQ SER_IRQ nLPCPD nCLKRUN VTR nIO_PME
IBM XT/AT-COMPATIBLE PARALLEL PORT
nSTROBE
nERROR
nSLCTIN
PD[7:0]
nDCD
BUSY
nDSR
nACK
nDTR
SLCT
nRTS
nCTS
nINIT
nALF
RXD
TXD
nRI
PE
LGP44-LGP47
LPC GPIO
XTAL1
LPC BUS
Clock CONFIGURATION REGISTERS VCC 24MHz Clock VTR
VTR
XTAL2 24MHz_OUT
SMB_A0 SCLK VTR SDAT nSMBINT
VTR SMBUS SMBus Isolation Circuitry
GP10-GP17 GP20-GP27 GP30-GP37 VTR GP50-GP57 SDAT_1 SDAT_2 SCLK_1 SCLK_2
GPIO
VTR
Figure 1 - LPC47N237 Block Diagram
Revision 0.3 (03-30-07)
Page 4
SMSC DB - LPC47N237
PRODUCT PREVIEW
Package Outline
Figure 2 - 100 Pin TQFP Package Outline Table 1 - 100 Pin TQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc
Notes: 1. 2. 3. 4. 5. Controlling Unit: millimeter. Tolerance on the position of the leads is 0.04 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. Details of pin 1 identifier are optional but must be located within the zone indicated.
MIN ~ 0.05 1.35 15.80 13.90 15.80 13.90 0.09 0.45 ~ 0 0.17 0.08 0.08 ~
o
NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~
MAX 1.60 0.15 1.45 16.20 14.10 16.20 14.10 0.20 0.75 ~ 7o 0.27 ~ 0.20 0.08
REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
SMSC DB - LPC47N237
Page 5
Revision 0.3 (03-30-07)
PRODUCT PREVIEW

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